ASIC Design and physical implementation

Job Description:

R&D Engineer position available in design and physical implementation of high performance System-On-Chip ASICs.

Key competencies required are:

Working experience in (digital) physical design implementation of large scale ASICs (Multi-100 million gates complexity).
Demonstrated ability in providing technical support to customers and managing customer working relationships
Demonstrated strong technical hands-on competency in using leading edge physical design EDA tools in projects.
In-depth CPU/DSP architecture/algorithm working knowledge and related physical design implementation knowledge is highly advantageous.
Utilize commercial and in-house EDA tools for the design and implementation of multi-100 million gate integrated circuits in 5nm or smaller advanced process nodes.
Opportunity to participate in innovation, design flow and methodology development to address challenges of designing in deep sub-micron processes and state-of-the-art ASIC design for AI/ computing and networking products

Qualifications : Requirements

Bachelors in Electrical/Electronics engineering with at least 8 years or more experience in a relevant field or Masters in Electrical/Electronics engineering with at least 6 years or more experience in a relevant field or PhD in Electrical/Electronics engineering with at least 3 years or more experience in a relevant field
Familiarity with VLSI design tools for Place&Route, Verilog simulation, DRC/LVS verification, Timing analysis (STA), Scripting languages - Tcl/Perl/ Python
Proficiency in UNIX/Linux

Work experience placement,